The graph model is utilized for new expression of global wiring information. 用得到的图模型来表示总体布线信息,从而可以在总体布局优化的同时估计布线对芯片面积的影响,并对总体布线进行调整。
Based on distributed RC and RLC transient response model, the methodology to optimize overall performance of global wiring in VLSI is proposed. 其次,在分布式RC模型和分布式RLC模型基础上,提出了一套优化顶层全局布线综合性能的设计方法,对设计高性能全局总线具有指导意义。